Responsible for the microarchitecture definition and RTL (register transfer level) development of

the CPU (central processing unit) functional, performance and power features. Specifically,

develop microarchitecture specifications and own the RTL development for CPU features in the

areas of instruction fetch and decode, branch prediction, instruction dispatch, integer and

floating-point execution, memory execution and the overall CPU power management. Use

domain knowledge to debug complex failure modes involving timeouts, data corruption, and

incorrect circuit operation. Use advanced VLSI circuits to improve efficiency, quality, and

performance. Collaborate with software and architecture teams to identify performance limiting

aspects of current software and hardware interactions. Use System Verilog HDL (hardware

description language) to model, design, simulate, test and implement electronic systems. Work

with verification, physical implementation, DFT (design for test) and firmware teams to deliver a

design which meets functional, performance, power, and area requirements.

• Master’s or foreign equivalent in Computer Engineering, Electronics Engineering, or a related field

• 2 years of experience in job offered or related occupation.

• 1. SystemVerilog, Verilog, and SystemVerilog Assertions.
• 2. Computer architecture and logic design principles.
• 3. Timing and area tradeoffs in a CPU microarchitecture.
• 4. RTL simulation and waveform debugging tools.
• 5. Low-power techniques including clock gating and power gating.

Worksite: 6433 Champion Grandview Way, Building 2, Ste 150, Austin, TX 78750

Applicant Instructions: Include job code 91557 in application. EOE